The present disclosure relates to a method and an apparatus as well as a computer program product for reducing signal edge jitter in an output signal from a numerically controlled oscillator.
Oscillators are used in many areas of signal processing. The use of numerically controlled oscillators has advanced as a result of the dissemination of binary digital information. Since binary signals do not contain any intermediate states between the two signal states, a realistic representation of analog signals can be achieved only using a suitably high sampling rate. The sampling rate is controlled using a resonant frequency of an excitable system which is capable of oscillation, such as a micromechanical oscillator or a ring oscillator. For this purpose, it is usually necessary to reduce the resonant frequency to a lower frequency.
When reducing the input frequency to the desired output frequency, undesirable side effects may result in signal interference. If the ratio of input frequency to output frequency is not an integer ratio, the output frequency may be output with edge fluctuation. This then results in phase noise, so-called jitter.
Phase locked loops (also referred to as PLLs), in particular, are widely used in telecommunications, control technology and metrology. Typical application examples are the (de)modulation of signals, clock recovery and the automatic tracking of the PLL output frequency in synchronism with an input signal of variable frequency which is noisy under certain circumstances. The latter is also used in the field of sensor systems, for example in micromechanical oscillators or rate-of-rotation sensors. The processing clock of the evaluation electronics is derived from the fundamental of the micromechanical oscillator or rate-of-rotation sensor using a PLL. As a result, filters and control circuits can be efficiently designed. In integrated circuits, purely digital PLLs allow particularly space-efficient implementations. The phase detector, loop filter and numerically controlled oscillator (NCO) are constructed from digital logic blocks. A crystal oscillator or a ring oscillator integrated in the circuit, for example, generates the basic clock fosc of the NCO.
One or more accumulators, which sum(s) a counter increment (dependent on the phase error, for example), can be used as the numerically controlled oscillator (NCO). If a predefined threshold value is exceeded, the counter overflows and starts the summation from the beginning. A counter run represents a clock period at the output of the NCO. Since the threshold value is generally not an integer multiple of the counter increment, a remainder is produced in the event of overflow, which remainder is concomitantly adopted or concomitantly taken into account in the next run in the case of an accumulator which continues to use the carry. The output clock of the PLL (called the system clock below) is thus on average only coupled to the input signal. The length of the individual clock periods may vary by 1/fosc, which is referred to as phase jitter.
US 2008/0069284 A1 describes a method for smoothing an output signal from a numerically controlled oscillator. In this case, a phase error of the output signal is determined and is reduced in a controllable delay module in order to obtain a smoothed output signal.